Title | Sl.No. | Module/Lecture |
| Design | I | Introduction |
1 | Introduction to Digital VLSI Design Flow Specification, High level Synthesis, RTL Design, Logic Optimization, Verification and Test Planning |
2 | Design Representation |
3 | Hardware Specific Transformations |
II | Scheduling, Allocation and Binding |
1 | Problem Specification: Scheduling, Allocation and Binding |
2 | Basic Scheduling Algorithms (Time constrained and Resource Constrained) |
3 | Allocation Steps: Unit Selection, Functional Unit Binding, Storage Binding, Interconnect Binding |
4 | Allocation Techniques: Clique Partitioning, Left-Edge Algorithm, Iterative Refinement. |
III | Logic Optimization and Synthesis |
1 | Heuristic Minimization of Two-Level Circuits: Espresso |
2 | Finite State Machine Synthesis |
3 | Multi-Level Logic Synthesis |
4 | Multi-Level Minimization |
5 | Technology Mapping |
| Verification | IV | Binary Decision Diagram |
1 | Introduction and construction |
2 | Reduction rules and Algorithms, ROBDDs |
3 | Operation on BDDs and its Algorithms |
4 | Representation of Sequential Circuits |
V | Temporal Logic |
1 | Introduction and Basic Operators |
2 | Syntax and Semantics of LTL, CTL and CLT* |
3 | Equivalence and Expressive Power |
VI | Model Checking |
1 | Introduction to Verification |
2 | Specification and Modelling |
3 | Model Checking Algorithm |
4 | Symbolic Model Checking |
5 | Automata and its use in Verification |
6 | Automata Theoretic Model Checking |
7 | Practical Examples with SMV |
| Test | VII | Introduction to Digital Testing |
1 | Introduction, Test process and Test economics |
2 | Functional vs. Structural Testing Defects, Errors, Faults and Fault Modeling (mainly stuck at fault modeling) |
3 | Fault Equivalence, Fault Dominance, Fault Collapsing and Checkpoint Theorem |
VIII | Fault Simulation and Testability Measures |
1-2 | Circuit Modeling and Algorithms for Fault Simulation
- Serial Fault Simulation
- Parallel Fault Simulation
- Deductive Fault Simulation
- Concurrent Fault Simulation
|
3 | Combinational SCOAP Measures and Sequential SCOAP Measures |
IX | Combinational Circuit Test Pattern Generation |
1 | Introduction to Automatic Test Pattern Generation (ATPG) and ATPG Algebras |
2 | Standard ATPG Algorithms
- D-Calculus and D-Algorithm
- Basics of PODEM and FAN
|
X | Sequential Circuit Testing and Scan Chains |
1 | ATPG for Single-Clock Synchronous Circuits
- Use of Nine-Valued Logic and Time-Frame Expansion Methods
- Complexity of Sequential ATPG
|
2-3 | Scan Chain based Sequential Circuit Testing
- Scan Cell Design
- Design variations of Scan Chains
- Sequential Testing based on Scan Chains
- Overheads of Scan Design
- Partial-Scan Design
|
XI | Built in Self test (BIST) |
1 | Introduction to BIST architecture BIST Test Pattern Generation, Response Compaction and Response Analysis |
2-3 | Memory BIST
- March Test
- BIST with MISR
- Neighborhood Pattern Sensitive Fault Test
- Transparent Memory BIST
|
